Chip scale package with heat spreader

ABSTRACT

A dense semiconductor flip-chip device assembly is provided with a heat sink/spreading/dissipating member which is formed as a paddle of a metallic paddle frame in a strip of paddle frames. Dice are bonded to the paddles by e.g. conventional die attach methods, enabling bump attachment and testing to be conducted before detachment from the paddle frame strip.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of application Ser. No. 09/342,789,filed Jun. 29, 1999, pending, which is a divisional of application Ser.No. 09/028,134, filed Feb. 23, 1998, now U.S. Pat. No. 6,314,639, issuedNov. 13, 2001.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to semiconductor device assemblies.More particularly, the invention pertains to a method for producing achip-on-board semiconductor device assembly with a heatspreading/dissipating member, and the device produced thereby.

2. State of the Art

In the design and production of modern integrated circuits (IC), animportant consideration is the dissipation of heat generated in thesemiconductor device. Elevated temperatures may cause irreparable damageto the die and its electrical connections.

Various methods for preventing excessive temperatures in a semiconductordevice have been in use.

Thus, for low-power devices of less than about I watt, the metal leadframe itself may be sufficient to dissipate generated heat. Lead frameconfigurations for improved heat dissipation are shown in U.S. Pat. No.5,541,446 of Kierse, U.S. Pat. No. 4,961,107 of Geist et al., and U.S.Pat. No. 5,101,465 of Murphy.

For higher power packaged devices, a metal heat spreader may beincorporated into the package or attached to the outside of the package.Because of the generally low thermal conductivity of polymers, the heatdissipation design is more critical for polymer-packaged devices thanfor those packaged in ceramic or metal.

The use of heat spreaders/heat sinks/heat dissipaters in packagedsemiconductor devices are often used to conduct heat to the exterior ofthe devices, either directly or via the leads. A wide variety of such isillustrated in U.S. Pat. No. 5,596,231 of Combs, U.S. Pat. No. 5,594,282of Otsuki, U.S. Pat. No. 5,598,034 of Wakefield, U.S. Pat. No. 5,489,801to Blish II, U.S. Pat. No. 4,024,570 of Hartmann et al., U.S. Pat. Nos.5,378,924 and 5,387,554 of Liang, U.S. Pat. No. 5,379,187 of Lee et al.,U.S. Pat. No. 4,507,675 of Fujii et al., U.S. Pat. No. 4,642,671 ofRohsler et al., U.S. Pat. No. 4,931,852 of Brown et al., U.S. Pat. No.5,173,764 of Higgins III, U.S. Pat. No. 5,379,186 to Gold et al., U.S.Pat. No. 5,434,105 to Liou, and U.S. Pat. No. 5,488,254 to Nishimura etal.

The above-indicated references may be characterized as providing complexdevices requiring difficult and/or costly processes to achieve thedesired heat dissipation. Most of the references are not applicable atall to a high density device attached in a bare state to a substratesuch as a circuit board.

Encapsulation compositions and methods are shown in U.S. Pat. No.4,358,552 to Shinohara et al. and U.S. Pat. No. 5,194,930 to Papathomaset al.

BRIEF SUMMARY OF THE INVENTION

The present invention comprises a high density semiconductor deviceassembly for electrical connection without wires to a substrate such asa circuit board. In a preferred embodiment, the invention comprises achip-on-board (COB) device with a heat spreader/dissipater on its backside. The active surface on its “front side” may be attached in a baredie state to the substrate by lead bond methods known in the art,preferably by ball-grid array (BGA) methods which simultaneouslycomplete each of the conductive bonds between die and circuit board.

The present invention also encompasses a “paddle frame” strip for (a)providing a heat spreader/dissipater on each die, (b) supporting thedice for die testing and/or (c) supporting the dice for applyingconductive bumps to the bond pads. The paddle frame strip mayincorporate any number of paddle frames, and preferably has at leasteight paddle frames.

The present invention further comprises a method for producing the highdensity semiconductor device with the heat spreader/dissipater.

The present invention provides significant advantages in the productionof dense semiconductor devices, including enhanced reliability, ease ofproduction, and reduced production costs.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The invention is illustrated in the following figures, wherein theelements are not necessarily shown to scale:

FIG. 1 is a plan view of a portion of a paddle frame and attachedsemiconductor dice of the heat spreading chip scale package of theinvention;

FIG. 2 is a cross-sectional side view of a die bonded to a paddle framein accordance with the heat spreading chip scale package of theinvention, as taken along line 2-2 of FIG. 1;

FIG. 3 is an enlarged perspective view of a semiconductor die bonded toa paddle of a paddle frame, furnished with a ball grid array and excisedfrom the paddle frame in accordance with the chip scale package of theinvention;

FIG. 4 is a side view of a circuit board upon which are reversiblymounted paddle-bonded semiconductor dice with ball grid arrays inaccordance with the heat spreading chip scale package of the invention;and

FIG. 5 is a cross-sectional side view of a circuit board upon which arereversibly mounted and resin-packaged, paddle-bonded semiconductor dicewith ball grid arrays, in accordance with the heat-spreading chip scalepackage of the invention.

DETAILED DESCRIPTION OF THE INVENTION

An improved high density semiconductor device assembly is provided bythe present invention which is configured to be electrically attached toa substrate such as a circuit board by array bonding. A series of baresemiconductor devices of the invention may be mounted on a substrate ina closely packed arrangement. The semiconductor device is provided witha heat sink/spreading/dissipating member. Following mounting on asubstrate, the device or plurality of devices may be “packaged” with aprotective polymeric sealer.

The semiconductor device assembly and a method for producing it aredescribed hereinbelow and illustrated in drawing FIGS. 1-5.

With reference to the drawings of FIGS. 1 and 2, a metal strip 10 ofheat conductive material is configured with multiple paddle frames 12.The metal strip 10 has left and right side rails 14, 16 and a series ofsprocket holes 18 in the side rails for precise positioning ofprocessing equipment and a plurality of semiconductor dice 20 which areattached to the metal strip. Each paddle frame 12 includes the siderails 14,16, cross-members 26, and a generally centrally positionedmetal paddle 22 which is attached to the side rails 14, 16 by paddlesupport bars 24 and to cross-members 26 by paddle support bars 28. Asemiconductor die 20, having a first major surface 36 and an opposingsecond major surface 38, has second major surface 38 attached to a metalpaddle 22 by die attach methods known in the art. Exemplary of suchsemiconductor die attachment methods is attachment using a semiconductordie attach layer 30 of electrically non-conductive polymeric adhesivesuch as epoxy or polyimide. Alternatively, a semiconductor die attachlayer 30 may be electrically conductive. As known in the art, a metalfilled polymer, an unfilled conductive polymer such as a silver filledepoxy or polyimide, or a conductive gold-silicon eutectic material maybe used. Thus, the semiconductor die attach layer 30 may be electricallyconductive or insulative, depending upon the circuit configuration ofthe second major semiconductor die surface 38. Thus, for example, thesecond major surface 38 may be designed to be grounded to a ground planesurface, which may be the metal paddle 22.

The metal paddle 22 acts as a heat spreader/dissipater in the finalsemiconductor device assembly 40. Thus, while the semiconductor dieattach layer 30 may be either electrically conductive or insulative, itpreferably has an enhanced heat conductivity. Where the metal paddle 22comprises a metal layer attached to a polymer layer, the semiconductordie attach layer 30 is attached to the metal surface 48 to enhance heattransfer (see drawing FIG. 3).

Each metal strip 10 with paddle frames 12 may be formed in the samemanner as are lead frames in the art. The number of paddle frames 12which may be incorporated into the metal strip 10 is limited only by thecapability of a manufacturer's machines for semiconductor die attachmentand die excising.

The paddle frame 12 includes the left and right side rails 14, 16 whichare joined by cross-members 26. The generally centrally located metalpaddle 22 is supported from the side rails 14, 16 and cross-members 26by paddle support bars 24, 28. Generally, no leads for electricalconduction are provided, although one or more of the paddle support bars24, 28 may be used as leads in certain specific instances. No narrow“leads” common in lead frames are required in the paddle frame 12,resulting in greater ease of manufacture and increased reliability.

The paddle frame 12 may be formed of a thin film of metal such asaluminum, silver, copper, or Alloy “42.” Typically, the metal paddle 22is sized to completely cover the second major surface 38 of thesemiconductor die 20 and preferably be somewhat larger. The thickness 44of the metal paddle 22 is a function of the quantity of generatedthermal energy, the semiconductor die size, the thermal conductivity ofthe semiconductor die attach material, and whether a packaging materialoverlies the metal paddle 22 in the final product. For generally lowrates of heat generation, the paddle thickness 44 may be the minimumrequired by structural considerations. However, where the heatgeneration rate is very high, it may be necessary to increase the paddlethickness 44 to provide an increased heat sink capacity.

In many cases, the thickness 44 of the metal paddle 22 need only besufficient to support the semiconductor die 20 prior to excision, andfor uniform adherence to the semiconductor die 20. The paddle thickness44 may typically range from about 0.5 μm to about 5 μm, but may varyfrom this range, particularly upwardly for enhancing heat sinkcapability. This range of paddle thickness 44 includes the typicalthicknesses of lead frames of the prior art. Paddle frames 12 may beformed and joined to semiconductor dice 20 by tape automated bonding(TAB).

To singulate each semiconductor device assembly 40, the paddle supportbars 24, 28 are excised close to the metal paddle 22 with excisions 50(see drawing FIG. 3).

Illustrated in drawing FIG. 1 is a plurality of semiconductor dice 20with conductive bond pads 32 on the first major surface 36, i.e. the“active” surface. While drawing FIG. 1 shows the conductive bond pads 32along the periphery of the semiconductor dice, thus limiting the numberof conductive bond pads, the invention may be used for semiconductordice having a full grid array of conductive bond pads as shown indrawing FIGS. 2 and 3.

In a preferred embodiment, conductive projections 34 such as solderbumps or balls are formed on the conductive bond pads 32, theprojections enabling “gang” bonding, i.e. flip-chip bonding, of thesemiconductor die bond pads to the conductive traces 46 of a substrate42 such as a circuit board. This is illustrated in drawing FIGS. 4 and5, which show a plurality of semiconductor device assemblies 40 flippedand bonded to circuit connections, e.g. conductive traces 46 (seedrawing FIG. 5), of a substrate 42 comprising a circuit board. Theinternal circuitry within the substrate 42 is not shown, beingirrelevant to the invention. The semiconductor device assemblies 40 maybe bonded to a substrate 42 in a high density pattern and, being “bare”semiconductor dice 20, take up minimal space. The bonding may becompleted by standard “flip-chip” methods, including thermal and/orpressure processes.

Each semiconductor device assembly 40 has a heatsink/spreader/dissipater 52 which was formerly a metal paddle 22 of ametal paddle frame 12. The heat sink/spreader/dissipater 52 has agenerally exposed surface 54 for dissipating heat generated in thesemiconductor device assembly 40.

As depicted in drawing FIG. 5, a sealant material 56 may be applied tothe periphery of a semiconductor device assembly 40 and the space 58between the semiconductor device assembly and the substrate 42. Thesealant material 56 seals the semiconductor device assembly 40 to thesubstrate 42 and protects the semiconductor device assembly frommoisture, etc. The spaces between adjacent semiconductor deviceassemblies 40 may be readily filled with sealant material 56. The space58 may be filled, for example, by injecting sealant material 56 throughholes, not shown, in the substrate 42. Preferably, surface 54 of theheat sink/spreader/dissipater 52 is largely left uncovered to providehigh heat dissipation.

Any sealant material 56 useful in packaging semiconductor deviceassemblies may be used, including e.g. epoxy, polyimide, etc.

A method of producing the semiconductor device assembly 40 includes thesteps of:

1. producing a plurality of semiconductor dice 20 with integratedcircuits as a wafer, each semiconductor die 20 having a first majorsurface 36 defined as an active surface with an array of conductive bondpads 32, i.e. input/output (I/O) pads, and a second, opposite majorsurface 38;

2. separating the individual semiconductor die 20 from the wafer;

3. providing a conductive “paddle frame” metal strip 10 with multiplepaddle frames 12, each paddle frame having a heat conductive metalpaddle 22 connected to side rails 14, 16 and cross-members 26 of thepaddle frame 12 by paddle support bars 24, 28;

4. bonding a semiconductor die 20 to each metal paddle 22 of the paddleframe metal strip 10 with a thin die attach layer 30 of adhesive oradhesive tape of e.g. epoxy or polyimide. The adhesive die attach layer30 may be provided with enhanced heat conductive properties.Alternatively, the second major surface 38 of the semiconductor die 20may be bonded to the metal paddle 22 eutectically by formation of e.g. agold-silicon eutectic die attach layer 30 or other electricallyconductive material such as a specially designed polyimide.

5. conductive projections 34, i.e. balls or bumps (stud bumps) forreflow may be formed on the I/O conductive bond pads 32 of thesemiconductor dice 20 either prior to or following attachment of thesemiconductor dice to the metal paddles 22;

6. the semiconductor dice 20 may be tested in sequence in strip form,i.e. while the metal paddles 22 with attached semiconductor dice areconnected to the paddle frame metal strip 10. A test head (not shown) isplaced to make temporary electrical connection with the conductive bondpads 32 or conductive projections 34 for the conduction of parametricand functional tests. The testing may include additional tests typicalof “burn-in” testing;

7. the paddle support bars 24, 28 connecting the metal paddles 22 to thepaddle frame 12 are excised to free each semiconductor device assembly40;

The semiconductor device assemblies 40 so produced are configured formounting in a “flip-chip” configuration, i.e. face down on a substrate42 such as a circuit board, e.g. by reflowing under heat and/or bypressure or other methods as known in the art.

The metal paddle 22 attached to the second major surface 38 of eachsemiconductor die 20 comprises a heat sink/spreader/dissipater 52 whichprevents overheating of the semiconductor device assembly 40 (a) duringtesting (including burn-in), (b) during mounting on the substrate 42,(c) during packaging, and (d) in actual operation.

Following attachment to a substrate 42 such as a circuit board, thesemiconductor device assembly 40 may be sealed with an electricallyinsulating sealant material 56 to produce a partially encapsulatedpackage. The exposed surface 54 of the heat sink/spreader/dissipater 52is preferably left largely uncovered, or is only thinly covered with thesealant material 56. The sealant may be any of the polymeric materialscommonly used for packaging, including those used for “glob-top.”Examples of such materials are epoxy resins and polyimides.

The invention is particularly applicable to high density integratedcircuit semiconductor device assemblies 40 having a large number ofinterconnections, i.e. conductive bond pads 32. Such devices may producesignificant quantities of thermal energy which, if not removed, may leadto destruction of the integrated circuit. The bare semiconductor dice 20of the invention may be densely mounted on a substrate 42 and thensealed by introducing a sealant material 56 between the substrate andsemiconductor dice to surround the electrical connections and the firstmajor or active surfaces 36 and edges 60 of the semiconductor dice 20.

Major advantages of the invention are as follows:

1. The ease of device handling is enhanced. The semiconductor dice 20are fixed to the unseparated metal paddles 22 of the “paddle frame” 12during the test process and each semiconductor device assembly 40 can behandled without touching the semiconductor die. Once the semiconductordevice assembly 40 is separated from the paddle frame 12 by excision ofthe paddle support bars 24, 28, the metal paddle 22 becomes a beatsink/spreader/dissipater 52, and the device may be handled and supportedsolely thereby.

2. Current methods of lead frame production may be used to produce thepaddle frame metal strip 10. The paddle frames 12 are much simpler indesign than lead frames, there being few or no electrical leads.

3. Semiconductor dice or multiple chips 20 may be mounted on a singlepaddle frame metal strip 10, using equipment widely used by devicemanufacturers. Thus, reliable attachment of the semiconductor dice 20 tothe metal paddles 22, testing (and burn-in) of the semiconductor dice,separation of the paddle mounted semiconductor dice from the paddleframe metal strip 10, and mounting of the semiconductor dice on asubstrate 42 may be easily accomplished using well-developed and commonassembly equipment and methods. The readily aligned semiconductor dieattach apparatus, test head, and lead excision apparatus enable accuracyand ease of operation in the device assembly.

4. The heat sink/spreader/dissipater 52 of the invention results inbetter temperature control and increased reliability of thesemiconductor device assembly 40.

5. Use of known technology and equipment results in a lower assemblycost. No additional specially-designed equipment is required.

6. A dense chip-size bare semiconductor device assembly 40 of lowprofile is produced for dense attachment to a circuit board or othersubstrate 42.

It is apparent to those skilled in the art that various changes andmodifications may be made to the semiconductor die with a heatspreader/dissipater and the novel method of manufacturing, testing andinstalling the semiconductor die of the invention as disclosed hereinwithout departing from the spirit and scope of the invention as definedin the following claims.

1. A semiconductor device assembly of a plurality of semiconductordevice assemblies, comprising: a semiconductor die having an activesurface having a plurality of bond pads thereon and an opposing secondsurface; at least one projection connected to at least one bond pad ofthe plurality of bond pads on the active surface of the semiconductordie for flip-chip bonding to a substrate, the at least one projectionincluding one of at least one solder ball and at least one solder bump;and a paddle frame of a plurality of paddle frames including a pair ofside rails, a plurality of cross-members, and a plurality of generallycentrally positioned paddles, the pair of side rails and the pluralityof cross members connected to a generally centrally positioned paddle ofthe paddle frame by a plurality of paddle support bars, the secondsurface of the semiconductor die being secured to the paddle, the paddlebeing attached to the side rail by at least two of the plurality ofpaddle support bars and being attached to the cross members by at leasttwo of the plurality of support bars.
 2. The semiconductor deviceassembly of claim 1, further comprising: an electrically conductiveadhesive layer securing said second surface of said semiconductor die tosaid generally centrally positioned paddle.
 3. The semiconductor deviceassembly of claim 2, wherein said electrically conductive adhesive layercomprises a eutectic material.
 4. The semiconductor device assembly ofclaim 2, wherein said electrically conductive adhesive layer comprises agold-silicon eutectic material.
 5. The semiconductor device assembly ofclaim 2, wherein said electrically conductive adhesive layer comprises ametal-filled polymer, said metal filling comprising a heat conductivematerial.
 6. The semiconductor device assembly of claim 2, wherein saidelectrically conductive adhesive layer comprises conductive polyimide.7. The semiconductor device assembly of claim 2, wherein saidelectrically conductive adhesive layer comprises a eutectic material. 8.The semiconductor device assembly of claim 7, wherein said electricallyconductive adhesive layer comprises a gold-silicon eutectic material. 9.The semiconductor device assembly of claim 2, wherein said electricallyconductive adhesive layer comprises a metal-filled polymer, said metalfilling comprising a heat conductor.
 10. The semiconductor deviceassembly of claim 2, wherein said electrically conductive layercomprises conductive polyimide.
 11. A semiconductor device assembly of aplurality of semiconductor device assemblies, comprising: asemiconductor die having an active surface having at least one bond padthereon and an opposing second surface; at least one projection securedto the at least one bond pad on the active surface of said semiconductordie for a flip-chip connection to a substrate, the at least oneprojection including one of at least one solder ball and at least onesolder bump; and a metal paddle from a paddle frame having no narrowcommon electrical leads for connection to the semiconductor die of aplurality of paddle frames connected by a pair of rails having aplurality of cross members therebetween, said second surface of thesemiconductor die being attached to the paddle, the metal paddleattached to at least one side rail by at least a plurality of paddlesupport bars and being attached to a plurality of cross members by thesupport bars, the paddle support bars not used for electrical leads forthe semiconductor die.
 12. The semiconductor device assembly of claim11, further comprising: an electrically conductive adhesive layersecuring said second surface of said semiconductor die to said generallycentrally positioned paddle.
 13. The semiconductor device assembly ofclaim 12, wherein said electrically conductive adhesive layer comprisesa eutectic material.
 14. The semiconductor device assembly of claim 12,wherein said electrically conductive adhesive layer comprises agold-silicon eutectic material.
 15. The semiconductor device assembly ofclaim 12, wherein said electrically conductive adhesive layer comprisesa metal-filled polymer, said metal filling comprising a heat conductivematerial.
 16. The semiconductor device assembly of claim 12, whereinsaid electrically conductive adhesive layer comprises conductivepolyimide.
 17. The semiconductor device assembly of claim 12, whereinsaid electrically conductive adhesive layer comprises a eutecticmaterial.
 18. The semiconductor device assembly of claim 17, whereinsaid electrically conductive adhesive layer comprises a gold-siliconeutectic material.
 19. The semiconductor device assembly of claim 12,wherein said electrically conductive adhesive layer comprises ametal-filled polymer, said metal filling comprising a heat conductor.20. The semiconductor device assembly of claim 12, wherein saidelectrically conductive layer comprises conductive polyimide.